Conventional memory devices store data bits in individually addressable memory cells arranged in rows and columns as a memory cell array. Read/write voltages are applied to individual memory cells using row and column electrodes referred to as word lines and bitlines, respectively. Associated with each port in the memory device, a typical memory cell array has one word line for each row of memory cells and one pair of complementary bitlines for each column of memory cells. Thus, a single-port memory would have a single word line associated with each row and a single pair of complementary bitlines associated with each column, while a dual-port memory would have two word lines associated with each row and two pairs of complementary bitlines associated with each column, and so on.
In order to obtain high memory density, memory cells are defined using small circuit areas. As a result, read/write signals propagating on one bitline can be coupled to one or more adjacent bitlines. Such coupling can be associated with inaccurate read/write operations, or can cause data loss in a memory cell. In particular, a write operation on a bitline is a relatively “strong” operation, driven directly by a strong buffer or single transistor. A bitline read operation, on the other hand, is relatively “weak,” driven through small, weak, access transistors of the memory cells. When a bitline being used for a write operation couples to a bitline used for a read operation, the read operation is almost always adversely affected such that the read operation may fail. While adjacent bitlines can be shielded using parallel electrodes that are connected to a supply voltage or ground, relying exclusively on such electrodes is undesirable in many applications because they occupy an appreciable amount of available circuit area.